1. Field of the Invention
The present invention relates generally to non-volatile memory devices, and more particularly, to charge trapping flash memories.
2. Description of Related Art
Electrically programmable and erasable non-volatile memory technologies based on charge storage structures known as Electrically Erasable Programmable Read-Only Memory (EEPROM) and flash memory are used in a variety of modern applications. A flash memory is designed with an array of memory cells that can be independently programmed and read. Sense amplifiers in a flash memory are used to determine the data value or values stored in a non-volatile memory. In a typical sensing scheme, an electrical current through the memory cell being sensed is compared to a reference current by a current sense amplifier.
A number of memory cell structures are used for EEPROM and flash memory. As the dimensions of integrated circuits shrink, greater interest is arising for memory cell structures based on charge trapping dielectric layers, because of the scalability and simplicity of the manufacturing processes. Memory cell structures based on charge trapping dielectric layers include structures known by the industry names Nitride Read-Only Memory, SONOS, and PHINES, for example. These memory cell structures store data by trapping charge in a charge trapping dielectric layer, such as silicon nitride. As negative charge is trapped, the threshold voltage of the memory cell increases. The threshold voltage of the memory cell is reduced by removing negative charge from the charge trapping layer.
Nitride read-only memory devices use a relatively thick bottom oxide, e.g. greater than 3 nanometers, and typically about 5 to 9 nanometers, to prevent charge loss. Instead of direct tunneling, band-to-band tunneling induced hot hole injection (BTBT HH) can be used to erase the cell. However, the hot hole injection causes oxide damage, leading to charge loss in the high threshold cell and charge gain in the low threshold cell. Moreover, the erase time must be increased gradually during program and erase cycling due to the hard-to-erase accumulation of charge in the charge trapping structure. This accumulation of charge occurs because the hole injection point and electron injection point do not coincide with each other, and some electrons remain after the erase pulse. In addition, during the sector erase of a nitride read-only memory flash memory device, the erase speed for each cell is different because of process variations (such as channel length variation). This difference in erase speed results in a large Vt distribution of the erase state, where some of the cells become hard to erase and some of them are over-erased. Thus the target threshold Vt window is closed after many program and erase cycles and poor endurance is observed. This phenomenon will become more serious when the technology keeps scaling down.
A typical nitride read-only memory flash memory cell structure positions a Oxide-Nitride-Oxide layer between a conducting polysilicon and a crystalline silicon semiconductor substrate. The substrate refers to a source region and a drain region separated by an underlying channel region. A flash memory cell read can be executed by a drain sensing or a source sensing. For source side sensing, one or more source lines are coupled to source regions of memory cells for reading current from a particular memory cell in a memory array.
A traditional floating gate device only store 1 bit per cell, but the advent of nitride read-only memory cells in which each nitride read-only memory cell provides 2 bits per flash cell that store charge in an Oxide-Nitride-Oxide (ONO) dielectric. In a typical structure of a nitride read-only memory cell, a nitride layer is used as a trapping material positioned between a top oxide layer and a bottom oxide layer. The ONO layer structure effectively replaces the gate dielectric in floating gate devices. The charge in the ONO dielectric with a nitrite layer may be either trapped on the left side or the right side of a nitride read-only memory cell.
A frequently used technique to program nitride read-only memory cells in a nitride read-only memory array is the channel hot electron injection method. During an erase operation, a common technique used to erase memory cells is called the band-to-band hot hole injection. The other side potential, from the side that is being erased, of a nitride read-only memory cell is likely to have a lateral electric field effect on the erase ability. Evaluating the endurance and retention of a nitride read-only memory array, the lack of uniformity in erase ability causes a margin loss due to cycling and baking. The other side of nitride read-only memory cells is floating (or connected to ground) which may be coupled to an uncertain voltage level (e.g. 1 volt or 4 volts), which causes a variation of the erase threshold of array cells. This in turn causes Vt distribution after an erase operation to be wider. The variation of uncertain voltage level may result in over-erasing. On the other hand, if the other side is connected to ground, a punch-through may cause the pump circuit to crash when the bit line bias is over the punch-through voltage. Consequently, during an erase operation of a block, the nitride read-only memory cells where some of the nodes are left floating may cause lack of uniformity in voltage level applied for erase the nitride read-only memory cells in a nitride read-only memory array.
As technology advances in flash memory devices, it is desirable to design a charge trapping flash memory cell structure that provides higher package density as well as superior device scalability.